icon are recognized as Speakers of Distinction. Over the past 15 years they have been identified by SMTAI attendees as giving the strongest technical presentations. Congratulations to each of these authors for a job exceptionally well done.

MONDAY, October 17
8:30am - 10:30am

ET1 Embedded Component Technology (ECT) - Ready for Prime Time
Chair: Steve Greathouse, Plexus Corporation
Co-Chair: Reza Ghaffarian, Ph.D., Jet Propulsion Laboratory
Monday, October 17 | 8:30am - 10:30am | 202B

The use of embedded active and passive components (sometimes referred to as embedded component technology (ECT) may be one of the most significant developments in the electronics industry since the IC package was invented. The use of embedded components gives significant improvements to product performance, and can even reduce cost. Moving the component from the outer surface of the PCB or device substrate into the inner layers reduces both lead-inductance and parasitic capacitance. In digital circuits, clock rates and signal rise time improves. In analog circuits, both bandwidth and signal rise times improve. What applications are driving the demand? Which companies are using the technologies? Is the infrastructure sufficiently developed? Has embedded technology reached the point of being cost effective? Attend this session and you will get the answers to these and many other questions related to the developing implementation of this technology.

Embedded Components on the Way to Industrialization
Hannes Stahr, Mark Beesley, AT&S

The Effect of Physical Dimensions of an Embedded Planar Capacitor on Reliability
Michael Azarian, Mohammed A. Alam, Michael G. Pecht, University of Maryland-CALCE

Embedding Components: Design and Process Implementation Principles
Vern Solberg, STC-Madison

Modular System Packaging by Embedding: Technologies, Applications and Perspectives
Lars Boettcher Speaker of Distinction

, S. Karaszkiewicz, A. Ostmann, Fraunhofer Institute IZM; D. Manessis, Thomas Loeher, Technical University of Berlin

HE1 Thermo-Mechanical Analysis and Prognostics of Lead-Free Solders for Harsh Environment Applications
Chair: John Evans, Ph.D., Auburn University
Co-Chair: Mike Bixenman, DBA, Kyzen Corporation
Monday, October 17 | 8:30am - 10:15am | Room 202A

This session explores the impact of harsh thermal and mechanical environments on lead-free solder alloys. In particular, the causes of specific failures are addressed, as well as, methods for prognostication for better reliability projections. The session places particular focus on grid array packages with a comparison to SnPb packages.

Reliability of Lead-Free LGA's and BGA's: Effects of Solder Joint Size, Cyclic Strain and Microstructure
Michael Meilunas, Universal Instruments Corporation

A New (Better) Approach to Tin Whisker Mitigation
Craig Hillman, Ph.D., Gregg Kittlesen, Randy Schueller, Ph.D., DfR Solutions

Prognostication of Remaining Life and Prior Thermo-mechanical Damage in Field-Deployed Electronics
Pradeep Lall, Ph.D., MBA Speaker of Distinction

, Mahendra Harsha, Krishan Kumar, Jeff Suhling, Kai Goebel, Auburn University

MONDAY, OCTOBER 17
11:00am - 12:30pm

ET2 Printing and Jetting Technologies for Electronics Applications
Chair: Lars Boettcher, Fraunhofer Institute IZM
Co-Chair: Steve Greathouse, Plexus Corporation
Monday, October 17 | 11:00am - 12:30pm | 202B

Printing and jetting technologies has moved from R&D to manufacturing in a wide range of commercial markets over the last years. Ink jet printing allows new opportunities for system assembly and integration. Different approaches for printing and jetting can realize interconnect structures; for example RFID, OLED or MEMS applications. Ink-Jet micro dispensing can also provide a highly accurate method as in drug delivery. Solder paste jetting can help to overcome the limits of conventional screen printing processes and realize ultra-fine dots and lines for the assembly of miniature components.

Printed Electronics Using Ink Jet Technology
Donald Hayes, Ph.D., MicroFab Technologies, Inc.

Printed Electronics and Nanomaterials
Alan Rae, Ph.D. Speaker of Distinction

, TPF Enterprises LLC

Solder Paste Jetting: A Practical Solution
Rita Mohanty, Ph.D. Speaker of Distinction

, Speedline Technologies

HE2 Metallization and Connector Failure Mechanisms
Chair: Pradeep Lall, Ph.D., MBA, Auburn University, NSF CAVE3 Electronics Research Center
Co-Chair: Dock Brown, Medtronic
Monday, October 17 | 10:30am - 12:00pm | 202A

In this session, various interconnect failure mechanisms will be presented with a focus on thermo-mechanical stresses, electromigration, and contact resistance degradation. Specifically, the papers present their findings on metallization and connector failure mechanisms. The first paper deals with electromigration in solder joints in automotive applications. The second paper examines Intermittent connector failures in electronic assemblies. The third paper examines the stability of aluminum thin films on flexible substrate under thermo-mechanical environments.

Electro-Migration and Material Transport in Solder Joints
Mathias Nowottnick, Andrej Novikov, University of Rostock; Andreas Fix, Robert-Bosch GmbH

Intermittent Connector Failures in Electronic Assemblies
Aravind Munukutla, Anil Kurella, Intel Corporation

Stability of Aluminum Thin Films on Flexible Substrate Under Thermal and Isothermal Conditions
Mohammad Hamasha, Tara Dhakal, Khalid Alzoubi, Awni Qasaimeh, Susan Lu, Ph.D., Charles R. Westgate, Ph.D., Binghamton University

MONDAY, OCTOBER 17
12:30pm - 1:30pm

ET Keynote Lunch
Chair: Reza Ghaffarian, Ph.D., Jet Propulsion Laboratory
Monday, October 17 | 12:30pm - 1:30pm | 202B

Illumination-Grade LED's: Roadmap and Challenges for Manufacturing
Ron Bonné, LC, Philips Lumileds Lighting Company

HE Keynote Lunch
Chair: Pradeep Lall, Ph.D., MBA, Auburn University
Monday, October 17 | 12:00pm - 1:30pm | 202A

How the Defense/Aerospace Industry is Responding to the Pb-Free (Lead-Free) Challenge
Anthony Rafanelli, Ph.D., P.E., Raytheon Integrated Defense Systems

MONDAY, OCTOBER 17
1:30pm - 3:00pm

ET3 Opportunities and Challenges in Solid State Lighting
Chair: Marc Chason, Marc Chason and Associates, Inc.
Co-Chair: Charles Woychik, Ph.D., Tessera, Inc.
Monday, October 17 | 1:30pm - 3:00pm | 202B

Solid State Lighting (SSL) products are entering the market place as alternatives to incandescent and fluorescent lamps. With rapidly expanding global market opportunities, supply chains are developing to address the product needs. LED based SSL assemblies require unique materials and assembly processes to produce long term reliability, while OLED based SSL luminaires require novel thin-film manufacturing methods. As a result, new manufacturing processes are evolving to drive lower cost assembly.

Low Voiding Reliable Solder Interconnects for LED Packages on Metal Core PCBs
Ellen Tormey, Ph.D., Rahul Raut , Westin Bent, Ranjit Pandher, Ph.D , Bawa Singh, Ravi Bhatkal, Ph.D., Cookson Electronics; Justin Kolbe, The Bergquist Company

Packaging Technologies for OLED Displays and Lighting Products
G. Rajeswaran, Ph.D., Moser Baer Technologies, Inc.

Failure Mechanisms for High Brightness LEDs
Randy Schueller, Ph.D. Speaker of Distinction

, Greg Caswell, DfR Solutions

HE3 Leaded and Lead-Free Component Solder Joint Reliability Testing
Chair: Mike Nadreau, Henkel Corporation
Co-Chair: John Evans, Ph.D., Auburn University
Monday, October 17 | 1:30pm - 3:00pm | 202A

This session will discuss the data collected during the testing of solder joints under mechanical loading as well as electrical components subjected to shock and vibration. Additionally, the results from a smart phone test vehicle plan will be shared. The test plan includes 01005 discrete and fine pitch CSP components that were subjected to thermal cycling, vibration and drop testing as well as failure analysis results.

Rework Challenges and Solutions for Solder Joints Under Constant Mechanical Load from Gold Plated EMC Springs
Wayne Zhang, Sven Peng, P.E., P. K. Pu, IBM Corporation; Hill Liu, Alec Chen, Tracy Cai, Wistron Corporation

Health Monitoring of Lead-Free Electronics Under Mechanical Shock and Vibration with Particle Filter Based Resistance Spectroscopy
Pradeep Lall, Ph.D., MBA Speaker of Distinction

, Ryan Lowe, Kai Goebel, Auburn University

Reliability Testing of Leading Edge Components for Handheld Portable Devices
Heather McCormick, P.E. Speaker of Distinction

, Jimmy Chow, Russell Brush, Craig Hamilton Speaker of Distinction

, Subramaniam Suthakaran, Mike Berry, Celestica Inc.

MONDAY, OCTOBER 17
3:30pm - 5:00pm

ET4 Evolving Technology and Current Issues Panel
FREE Beer and Pretzels! Chair: Reza Ghaffarian, Ph.D., Jet Propulsion Laboratory
Co-Chair: Marc Chason, Marc Chason and Associates, Inc.
Monday, October 17 | 3:30pm - 5:00pm | 202B

ET cannot go home without answering your most challenging questions. So, come and join the team of industry experts to learn even more about where the technology is heading and the current key issues in packaging, SMT, LED, Solar and printed electronics. Experts from industry will present an overview of current and future technology, current status of solar and the SMT relationship. Bring your challenging issues/questions from work to get answers from experts who provide unique perspectives based on their experience.

Panelists:

Charles Woychik, Ph.D., Tessera, Inc.,
(Packaging Trends)

Alan Rae, Ph.D., TPF Enterprises LLC,
(Nanotechnology)

Steve Greathouse, Plexus Corporation,
(Advanced Packaging Technologies)

Irene Sterian, P.E., Celestica Inc.,
(Solar Energy and SMT)

Lars Boettcher, Fraunhofer Institute IZM,
(Embedded Die Technology/Europe)

HE4 Reliability of SAC Solder Joints
Chair: John McMahon, Celestica Inc.
Co-Chair: Tom Borkes, The Jefferson Project
Monday, October 17 | 3:30pm - 5:00pm | 202A

While considerable progress has been made in understanding the reliability of assemblies manufactured using SAC alloys, much remains to be done. This session looks at three different aspects of SAC reliability - the performance of SAC relative to tin/lead for an unusual component, the effect of thermal aging on copper-tin intermetallics, and the reliability of joints formed from different SAC alloys in thermal cycling and drop testing.

Reliability of Mixed Alloy Ball Grid Arrays Under Thermal Fatigue and Drop Shock
Ranjit Pandher, Ph.D., Ashok Pachamuthu, Cookson Electronics

Effects of Aging on the Secondary Intermetallic Layer (Cu3Sn1) for SAC 305 Solder
Kelsey Fitzgerald, Jay Marshall, Teneil Ryno, Andrew Kelley, Dana Medlin, Ph.D., South Dakota School of Mines and Technology; Clay Voyles, Radiance Technologies Inc.

Surface Mount Attachment Life Testing of a RF Circulator Component Assembled with Pb-free of SnPb Solder
Richard Coyle, Ph.D. Speaker of Distinction

, Robert Kotlowitz, Peter Read, Richard Popowich, Alcatel-Lucent; Robert Quigley, Robert O'Neill, M/A-COM Technology Solutions

TUESDAY, OCTOBER 18
10:30am - 12:30pm

AAT1 QFN Assembly and Reliability
Chair: Andrew Mawer, Freescale Semiconductor
Co-Chair: Viswam Puligandla, Ph.D., Nokia (Retired)
Tuesday, October 18 | 10:30am - 12:30pm | 202B

This session will cover the assembly and reliability of Quad Flat Pack No Lead (QFN) packages which are sometimes referred to as Bottom Termination Components (BTC). The first paper will outline the benefits and also the challenges of using QFNs which can include voiding, opens, shorts, insufficients and entrapped flux volatiles. The second paper will focus on the board-level reliability of QFN when used with various Pb-free alloys with comparisons to SnPb. Lastly, the issue of QFN thermal pad solder voiding will be addressed in detail with a focus on how thermal performance of the package is affected.

Overcoming the Challenges of QFNs
Karl Seelig, Kevin Pigeon, AIM

Temperature Cycling Performance of a Quad Flat No Lead (QFN) Package Assembled with Multiple Pb-Free Solders
Richard Coyle, Ph.D. Speaker of Distinction

, Peter Read, Richard Popowich, Debra Fleming, Alcatel-Lucent; Heather McCormick, P.E. Speaker of Distinction

, Celestica Inc.

Considerations for QFN Thermal Pad Solder Coverage
Thomas Adams, Plexus Corporation

Minimizing Voiding in QFN Packages Using Solder Preforms
Seth Homer and Ron Lasky, Ph.D., P.E. Speaker of Distinction

, Indium Corporation

SMT1 Stencil Printing Solutions for Next Generation, Fine Pitch Components
Chair: Brian Roggeman, Universal Instruments Corporation
Co-Chair: Glenn Robertson, Process Sciences, Inc.
Tuesday, October 18 | 10:30am - 12:00pm | 202C

Current industry trends are towards miniaturization, with very fine pitch components such as 0.3mm pitch and 01005 devices emerging to increase functionality while minimizing footprint. Often times fine pitch components are included in the same product as much larger components, and this further escalates stencil printing challenges. Novel solutions in the area of stencil materials and design and squeegee technology are proposed to satisfy the requirements of these complex assemblies.

Evaluation of Stencil Foil Materials, Suppliers and Coatings
Chrys Shea Speaker of Distinction

, Shea Engineering Services; Ray Whittier, Vicor Corporation

The Development of a 0.3mm Pitch CSP Assembly Process Using Standard Materials
Clive Ashmore Speaker of Distinction

, Mark Whitmore Speaker of Distinction

, DEK Printing Machines Ltd.

Effect of Stencil Technology on Ultra Fine Pitch Printing
S. Manian Ramkumar, Ph.D., Speaker of Distinction

Rochester Institute of Technology; Rita Mohanty, Ph.D., Speaker of Distinction

Speedline Technologies

MFX1 Solar Module Manufacturing
Note: this session switched with BUS1.
Chair: Chrys Shea, Shea Engineering Services
Co-Chair: Irene Sterian, P.E., Celestica Inc.
Tuesday, October 18 | 10:30am - 12:00pm | 104

Solar module manufacturing processes share many similarities with surface mount technology, including stencil printing and automated soldering. As the manufacturing of solar modules and related electronics expands to meet increasing market demands, the needs to reduce cost, boost throughput and improve reliability become more pronounced. Many of the scientific tools and techniques that brought SMT to its current level of technology can also be applied to the solar manufacturing arena.

Photovoltaic Industry Overview and Comparison of Global Business Models
Matthew Holzmann, Christopher Associates

Lead-Free Solders for Use in Solar Module Manufacturing
Christiaan Mey, Anthony Cao, Dough D. Perovic, University of Toronto

Screens and Electroformed Accuscreens for Solar Printing Applications
William Coleman, Photo Stencil

EMS Global Strategies for Lowering EMS Costs
Chair: Sue Mucha, Powell-Mucha Consulting, Inc.
Co-Chair: Mike Buetow, CIRCUITS ASSEMBLY Magazine
Tuesday, October 18 | 10:30am - 1:00pm | 204A

The nature of outsourcing is changing due to greater awareness of the risks from geopolitical events, local legislation, and natural disasters. This session, aimed at OEMs, and EMS program managers and executives, looks at risk mitigation strategies from Asia to Eastern Europe, and selected SMT processing solutions that could benefit those companies grappling with RoHS and other environmental or leading-edge (high BGA pin count) technical issues.

Eastern European EMS Site Location Options: Why Kimball Electronics Saw Poland as the Best Choice
Tom Ferris, Kimball Electronics Group

Technical Trends in Networking from a Manufacturing Perspective
Roger Hung, Tailyn Communication Company, Ltd.

Driving Improvements in Quality, Delivery and Cost in High Mix, Low Volume Manufacturing Operations
Kevin Camelon, Fabrinet

How Can Vapor Phase Technology Support EMS RoHS Challenges
Jochen Lipp, IBL Technologies, LLC

Speaker Panel - Building an EMS Cost Model

TUESDAY, OCTOBER 18
2:00pm - 3:30pm

AAT2 Assembly Solutions for Next Generation Package on Package (PoP) Requirements
Chair: Lee Smith, Amkor Technology
Co-Chair: Sheldon Schwandt, Research In Motion
Tuesday, October 18 | 2:00pm - 3:30pm | 202B

Over 350 million PoP components were stacked last year with top BGA densities of 0.65 to 0.5mm and bottom densities at 0.5 to 0.4mm pitch. With the wide application of PoP in smartphone and media tablets, both BGA interfaces require pitch reduction to support higher processor and memory speeds in thinner PoP stacks. This is driving a range of next generation PoP technologies that require new assembly solutions in SMT stacking.

Package-on-Package (PoP) Assembly Challenges and Solutions for Low-Volume Engineering Prototype and Test Applications
Deborah Dressler, Ming Li, Donald Mullen, Rambus Inc.

SMT Process Characterization for Package on Package Interposer (PoPI)
Dudi Amir and Karan Kacker, Intel Corporation

0.4mm PoP Assembly Development and Reliability
Mark Schwarz, Alan Choi, Owen Fay, Milind Shah, Qualcomm

SMT2 Head-in Pillow: Solder Paste Development, Component Warpage Measurement and Case Studies
Chair: Jasbir Bath, Bath Technical Consultancy
Co-Chair: Derek Daily, Senju Comtek Corporation
Tuesday, October 18 | 2:00pm - 3:30pm | 202C

Head-in-pillow component soldering defects are a continuing concern in the industry. The session will look at thermal stability of solder paste during reflow and its role in producing as well as mitigating this defect. Newly developed projection moire technology to measure temperaturedependent component warpage will be described using case studies from advanced packaging and process development. Information will be presented on evaluating thinner packages with higher outgoing package co-planarity to try and meet SMT and rework capability according to JEDEC standards.

Understanding Head-in-Pillow Defects – The Role of Thermal Stability in Paste
Ranjit Pandher, Ph.D., Rahul Raut, Michael Liberatore, Cookson Electronics

Projection Moiré vs. Shadow Moiré for Warpage Measurement and Failure Analysis of Next Generation Packages
Joe Thomas, ZN Technologies

Defining Package Warpage Criteria to Mitigate Head and Pillow Defects
Paramjeet Singh Gill, Yoong Ta Chin, Intel Corporation

BUS1 Supply Chain Management: Modeling, Processes, and Obsolescence
Note: this session switched with MFX1.
Chair: Gary Tanel, Electronics Alliance
Co-Chair: Jim Baker, Spectra Sales Corporation
Tuesday, October 18 | 2:00pm - 4:00pm | 202D

As the supply network evolves on a global scale, we find that it is critical to understand the total costs through modeling the systems and providing processes that can proactively plan. Don't get caught by surprise. You will also gain insights into planning for obsolescence part management. This session is best suited for purchasing and engineering managers.

Achieving the Excellent SCM: Diary of a Practitioner Wearing the EMS and OEM Shoes
Harjinder Ladhar Speaker of Distinction

, Microsoft Corporation

How to Calculate the True Cost of Global Electronics Outsourcing
Eric Miscoll, Charlie Barnhart & Associates

A Practical Approach to Dealing With Obsolescence Mitigation
James Carrigan, Premier Semiconductor Services, LLC

How to Protect Your Program Profit Plan in the Reality of Obsolesce
Laurence Pappas, J.D., Channel One International

ENV Environmental Challenges That Affect the Global Supply Chain
Chair: Rob Rowland, RadiSys Corporation
Co-Chair: Daniel F. Baldwin, Ph.D., Engent, Inc.
Tuesday, October 18 | 2:00pm - 3:30pm | 104

Global supply chain challenges due to natural disaster or environmental legislation is a growing concern. How much do you really know about the upcoming RoHS recast and recent changes to the RoHS exemptions? How will these changes impact you? Are you concerned about natural disasters and their impact to your supply chain? This session will provide information about the RoHS recast (i.e. RoHS 2), the current state of RoHS exemptions and how companies can prepare for natural disasters.

RoHS Recast - Ready or Not?
Krista Crotty, Alberi EcoTech

EU ROHS Exemptions, Technology and Trends Since Promulgation
Jacklin Adams, Marie Cole, Mary Beth Fletcher, George Galyon, Curtis Grosskopf, John Quick, Sophia Lau, IBM Corporation

Natural Disasters and Business Disruption: How Can Electronics Companies Evaluate and Mitigate Their Risk
Harvey Stone, Triple Bottom Line Times

TUESDAY, OCTOBER 18
4:00pm - 5:30pm

AAT3 Process and Reliability Characterization of PoP Materials and SMT Processes
Chair: Sheldon Schwandt, Research In Motion
Co-Chair: Lee Smith, Amkor Technology
Tuesday, October 18 | 4:00pm - 5:30pm | 202B

To ensure PoP packages do not become a limiting factor in new designs there needs to be a way to achieve lower profile solutions, the exploration of lower standoff solder joints and modified mold cap via's will be reviewed in the context of final collapsed height and resulting reliability. To continue improving the reliability and yields of PoP assemblies in HVM manufacturing, the right materials and process parameters need to be selected. The authors will present on material choices and SMT process parameters and their impact on reliability and manufacturing impact.

Material Selection and Parameter Optimization for Reliable TMV PoP Assembly
Brian Roggeman, David Vicari, AREA Consortium, Universal Instruments Corporation; Lee Smith, Ahmer Syed, Amkor Technology

Evaluation of Reliability and Stack-Up Height on Next Generation 0.5mm Pitch PoP Packages
Mark Schwarz, Alan Choi, Owen Fay, Qualcomm

0.3mm Pitch CSP Process Development and Printed Circuit Board (PCB) Design
Jonas Sjoberg Speaker of Distinction

, Jenson Lee, Ranilo Aranda, David Geiger, Flextronics Advanced Technology Group

SMT3 Lead-Free Rework and Repair Solutions for Today's Challenges
Chair: Alan Donaldson, Intel Corporation
Co-Chair: Jasbir Bath, Bath Technical Consultancy
Tuesday, October 18 | 4:00pm - 5:30pm | 202C

Rework and repair continues to be a challenge because of the addition of lead-free soldering temperatures. With board features becoming more complex, changes in rework and repair processes are needed. These three papers represent a wide variety of solutions to the most common rework and repair challenges at hand.

BGA Rework Challenges of High Thermal Mass, Large PCBA's
Manivannan Sampathkumar, Gopinath Aravindakshan, Dale Lee Speaker of Distinction

, Plexus Engineering Solutions; Denis Jean, Plexus Manufacturing Technology

Reworking of Pin Through Hole Components Using "Hot Air" Paste in Hole Process
Guhan Subbarayan, Ph.D., Cisco Systems; Leo Anderson, Flextronics International

An Innovative Rework Solution To Assembled IC Components
Mary Liu, Ph.D., Wusheng Yin, Ph.D., YINCAE Advanced Materials, LLC; Mark J. Walz, Training and Tooling Associates

MFX2 Void Reduction in Lead-Free Soldering Processes
Chair: Simin Bagheri, Celestica Inc.
Co-Chair: Leo Devine, Indium Corporation
Tuesday, October 18 | 4:00pm - 5:00pm | 202D

Pb-free solder joints are more prone to voiding than tin-lead joints due to a variety of contributing factors. Significant research has been conducted into the cause of voiding and its effect on the long term reliability of the resulting solder joints. Developing a solder paste and assembly process with low voiding is of interest to the electronics industry.

Voiding Control at QFN Assembly
Derrick Herron, Yan Liu, Ph.D., Ning-Cheng Lee, Ph.D., Indium Corporation

Lead-Free Paste Characterization (Wetting & Voiding) vs. Reliability
J. Trodler, W.C. Heraeus GmbH, Hans-Juergen Albrecht, Ph.D., Speaker of Distinction

Siemens AG;

SUB1 Challenges and Solutions for PCB Technology
Chair: Gil White, DDi Global
Co-Chair: Laura Turbini, Ph.D., Research in Motion
Tuesday, October 18 | 4:00pm - 5:30pm | 104

Next generation Printed Circuit Board (PCB) technologies are the key to success for design, fabrication and assembly of PCBs. This session will discuss challenges with the co-planarity of both the substrate package and the PCB motherboard, it will also address the question - can room temperature co-planarity measurements predict co-planarity at Lead-Free assembly temperatures? Also, a discussion of challenges and solutions for filling of through holes and blind microvias with an copper electroplating process to provide a thermal path or a planar surface for assembly. Additionally, this session will discuss the process, and how to quantify and benchmark PCB suppliers in terms of process capability, quality, and relative reliability for ATE PCBs.

PCB Dynamic Co-Planarity at Elevated Temperatures
John Davignon, Intel Corporation; Ken Chiavone, Jahui Pan, Akrometrix; James Henzi, Cisco Systems; David Mendez, Ron Kulterman, Flextronics, all members of the iNEMI SMT Co-Planarity Work Group

New Challenges for Higher Aspect Ratio: Filling Through Holes and Blind Micro Vias with Copper by Reverse Pulse Plating
Bernd Roelfs, Ph.D., Nina Dambrowsky, Christof Erben, Stephen Kenny, Atotech GmbH

Benchmarking and Qualifying Printed Circuit Board Fabricators for Semiconductor Device Test Boards
William J. Mack, Texas Instruments, Inc.

WEDNESDAY, OCTOBER 19
8:00am - 10:00am

AAT4 Reliability I - Impact of Materials and Design
Chair: Randy Schueller, Ph.D., DfR Solutions
Co-Chair: Adriana Porras, Freescale Semiconductor
Wednesday, October 19 | 8:00am - 9:30am | 202B

Electronics reliability continues to be an area of critical importance. This session contains three extremely important, yet widely different papers. The first paper addresses the significant impact that copper has on the properties of Sn-Ni intermetallic. Next, the reliability of 0.4 mm pitch packages is covered along with process and design changes that can be employed to enhance the reliability. The final paper presents work done to develop a new fast flow reworkable underfill that can be cured quickly.

Intermetallic Fragility on ENIG Upon Addition of Limitless Cu
Martin Anselm, Ph.D., Brian Roggeman, Universal Instruments Corporation

Processing Strategies and Reliability of 3D Wafer Level CSPs
Fei Xie, Ph.D., Zhaozhi Li, Ph.D., Auburn University; Daniel F. Baldwin, Ph.D., Speaker of Distinction

Paul N. Houston, Speaker of Distinction

Brian J. Lewis, Engent, Inc.

A Novel Low Temperature Fast Flow and Fast Cure Reworkable Underfill
Mary Liu, Ph.D., Wusheng Yin, Ph.D., YINCAE Advanced Materials, LLC

SMT4 Vapor Phase Soldering - Reflow to Rework Applications, 3 Case Studies
Chair: David Suihkonen, R&D Technical Services
Wednesday, October 19 | 8:00am – 9:00am | 202C

This session will present three case studies for the uses of Vapor Phase Reflow and Rework. From tin whisker mitigation improvement for reflow, to high reliability solder reflow, to vapor phase used as a rework process. This session will cover a variety of vapor phase uses, the process requirements and benefits and will shed light on many of the discussion points currently revolving around vapor phase. Challenges for the three case studies will be revealed and solutions presented. This will be a very interesting session.

A Case Study on Process Improvements for Vapor Phase Rework on High Thermal Mass SMT Connector
Rupen Trivedi, Brian Standing, Celestica Inc.

In-process Reduction/Mitigation of Tin Whiskers by Condensing Vapor Reflow
Anthony Primavera, Ph.D. Speaker of Distinction

, Micro Systems Engineering

Void-Free Soldering in Vapor Phase Reflow
John Bashe, Rehm Thermal Systems LLC

MFX3 Lower Cost Alternative Lead-Free Alloys for Electronic Assembly
Chair: Peter Biocca, P.E., ITW Kester
Co-Chair: Ray Chartrand, CharTrain Consulting
Wednesday, October 19 | 8:00am - 9:30am | 202D

As the demand for higher priced metals traditionally used in lead-free soldering materials continue to escalate, lower cost solder alloy options become more interesting to assemblers around the world. In some cases these alternative alloys also reduce the risks of some types of premature failures and may reduce reliability concerns over traditional lead-free alloys. This session will explore several of these lower cost solder options that can be used in wave soldering, selective and solder paste applications.

Choosing a Low Cost Alternative to SAC Alloys for PCB Assembly: Preliminary Work
Brook Sandy, Ron Lasky, Ph.D., P.E. Speaker of Distinction

, Indium Corporation

The Effect of Microalloy Additions on the Morphology and Growth of Interfacial Intermetallic in Low-Ag and No-Ag Pb Free Solders
Keith Sweatman Speaker of Distinction

, Tetsuro Nishimura, Nihon Superior Co., Ltd.; Jonathan Read, Kazuhiro Nogita, University of Queensland

A Unique Low-Ag Alloy Solder Paste for High-Reliability SMT Applications
Masato Shimamura, Tsukasa Ohnishi, Tomoko Nonaka, Seiko Ishibashi, Senju Metal Industry Co. Ltd.; Tetsuya Okuno, Satoru Akita, Derek Daily, Senju Comtek Corporation

BUS2 Supply Chain Management Via Predictive Cost and Assembly Process Modeling
Chair: Dale Lee, Plexus Corporation
Co-Chair: PK Pu, IBM China Procurement
Wednesday, October 19 | 8:00am - 9:30am | 104

Globalization, shorter time to market, regional disasters and shorter product life cycles have placed greater emphasis on management of supply chains to ensure product availability and profitability. This session will address the use of supply chain modeling for design cost drivers, materials should cost/real cost comparisons, and assembly impacts in the development and/or early production process.

Supply Chain Management Through Cost Modeling
Alan Palesko, SavanSys Solutions LLC

Improving Supply Chain Performance Using Business Intelligence and Specialized Software Tools Proactively
Harsh (Hersh) Kohli, ZenSar Technologies

Dynamic Production Planning
Jay Gorajia, Mentor Graphics-Valor Division

SUB2 New Surface Finish Chemistries / Chemical Tests
Chair: Raiyo Aspandiar, Ph.D., Intel Corporation
Co-Chair: Norman Armendariz, Ph.D., Texas Instruments
Wednesday, October 19 | 8:00am - 10:00am | 204A

PCB surface finishes are key materials in board assembly technology and efforts to enhance their properties, technically, economically and environmentally, continues within the industry. This session contains a presentation on a new surface finish that uses organic metal technology. Ionic and oxides are omnipresent on the surfaces of boards. Sometimes, they are expected to be there, such as activators from the soldering fluxes. Other times, these ionic species can act as contaminants. In any case, it is of paramount importance that these ionic and oxide species can be detected, and quantitatively measured to ensure board product quality and reliability. This session contains three additional presentations that expound on chemical and electrochemical tests that quantitatively measure the oxide or ionic content on the surface of PCBs.

Analysis of Corrosion Films in Printed Circuit Board Assemblies
Anil Kurella, Ph.D., Balu Pathangey, Ph.D., Tim Ciarkowski, Zhiyong Wang, Intel Corporation

Silver Nitric-An Innovative Process Indicator for Oxidation of PCB with OSP Finish
Eric Hou, D. F. Chung, Paul Wang, Ph.D. Speaker of Distinction

, Mitac International Inc.

Correlation of SIR Halide Halogen and Copper Mirror Tests
Nicole Palma, Ron Lasky, Ph.D., P.E. Speaker of Distinction

, Indium Corporation

WEDNESDAY, OCTOBER 19
10:30am - 12:00pm

AAT5 Reliability II - Understanding Solder Joint Performance
Chair: Marie Cole, IBM Corporation
Co-Chair: Scott Buttars, Intel Corporation
Wednesday, October 19 | 10:30am - 12:00pm | 202B

Understanding the contributions of design parameters, package materials, solder alloy and solder joint geometry to solder joint reliability can be challenging. Additionally, it may be difficult to extrapolate the results from various laboratory test conditions to actual product field conditions. This session will share data assessing these contributing factors for several types of area array packages and an interpretation of the data for various product applications.

Quick Assessment of the Minimum Peak Reflow Temperature Required in Low-Ag Solder Assembly
Pericles A. Kondos, Michael Meilunas, and Brian Roggeman, AREA Consortium-Universal Instruments; and Peter Borgesen, Binghamton University

Comparing Electronic Component Package Materials and Substrate Vendors for Solder Joint Reliability Improvements
Thomas Koschmieder, Ph.D., Speaker of Distinction

Joachim Rayos, Burton Carpenter, Gary Westerman, Freescale Semiconductor, Inc.

Damage Mechanisms and Acceleration Factors for No-Pb LGA, TSOP and QFN Type Assemblies in Thermal Cycling
Luke Wentlent, Babak Arfaei, Binghamton University; Michael Meilunas, Liang Yin, Universal Instruments Corporation

AAT6 Challenges of Assembly of 3D Stacked and Conventional Flip Chip Packages
Chair: Charles Woychik, Ph.D., Tessera, Inc.
Co-Chair: Marc Chason, Marc Chason and Associates, Inc.
Wednesday, October 19 | 10:30am - 12:00pm | 104

This session will discuss the processing and reliability strategy to provide a cost effective 3D wafer level CSP packaging solution. A detailed analysis of the yield will be presented along with different underfill processing methods that were used to resolve the underfill encroachment issue on fine pitch packages. In addition, the challenges associated with the implementation of through silicon vias (TSV) for 3D IC packaging will presented. Finally, an investigation of the effects of several assembly process parameters on warpage will be overviewed. This work shows how an effective model can be used to optimize the process in order to minimize warpage and improve both yield and reliability.

Processing Strategies and Reliability of 0.4 mm Pitch CSPs
Daniel F. Baldwin, Ph.D., Speaker of Distinction

Paul N. Houston, Speaker of Distinction

Brian J. Lewis, Engent, Inc.; Fei Xie, Ph.D., Auburn University

Implementing TSV for 3D Semiconductor Packaging
Vern Solberg, STC-Madison

Flip Chip Assembly Process Optimization and Material Selection Through Validated Simulations
Ron Zhang, Ph.D., Rajesh Katkar, Michael Huynh, Laura Mirkarimi, Tessera, Inc.

SMT5 Cleaning Interactions With Assembly Processes
Chair: Dave Hillman, Rockwell Collins
Co-Chair: Dave Watson, Unilife
Wednesday, October 19 | 10:30am - 12:00pm | 202C

Ignorance of the interactions of assembly processes and materials is the fastest path to poor process yields. This session is focused on three critical segments of the assembly process: solder paste printing, solder joint reflow and secondary assembly contamination sources. Session attendees will hear about cleaning interactions of nanocoated stencils, vapor phase versus reflow process flux residue comparisons and the "unlikely but real" assembly contamination sources.

Compatibility of Cleaning Agents with Nano-Coated Stencils
David Lober, Mike Bixenman, DBA, P.E. Speaker of Distinction

, Kyzen Corporation

Reliability and Cleanability of Solder Paste Residue: Vapor Phase vs. Convection
Emmanuelle Guene, Marie Verdier, INVENTEC

Thinking Inside the Bag on Cleanliness
Eric Camden, Foresite, Inc.

MFX4 Alternate Lead-Free Alloys: Materials and Processes
Chair: Ron Lasky, Ph.D., P.E., Indium Corporation
Co-Chair: Alan Rae, Ph.D., TPF Enterprises
Wednesday, October 19 | 10:30am - 12:00pm | 202D

For a few years it appeared that the electronics assembly industry might settle on SAC305 as the alloy of choice for SMT lead-free assembly. More recent developments have established that SAC105 provides improved drop shock performance. Earlier work had shown that small quantities of dopants dramatically improved the performance of SnCu wave solder alloys and more recently that other dopants can improve the performance of SAC105. The confluence of these and other findings have resulted in considerable new work on alternate lead-free alloys. The papers in this session will address some of these and other issues.

High Temperature Lead-Free Solder Joints Via Mixed Powder System
Hongwen Zhang, Ph.D., Ning-Cheng Lee, Ph.D. Speaker of Distinction

, Indium Corporation

Developing a Pb-Free Solder Through Micro-Alloying
Srinivas Chada, Ph.D., Mark Currie, Ph .D., Hector Steen, Ph.D., Brian Toleno, Ph.D. Speaker of Distinction

, Richard Boyle, Henkel Electronic Materials, LLC

An Investigation Into Low Silver Lead-Free Alloy Solder Paste for Electronics Manufacturing Applications
Jasbir Bath Speaker of Distinction

, Christopher Associates/Koki Solder; Manabu Itoh, Gordon Clark, Kimiaki Mori, Hajime Takahashi, Koki Solder; Roberto Garcia, Christopher Associates

SUB3 Surface Finish for Assembly and Reliability
Chair: Don Banks, St. Jude Medical
Co-Chair: Viswam Puligandla, Ph.D., Nokia (Retired)
Wednesday, October 19 | 10:30am - 12:00pm | 204A

Surface finish is a key element in any board or substrate value proposition. In this session an ENEPIG board finish is discussed. Five finish thicknesses from two suppliers are evaluated for an aerospace application. Next, a palladium on copper surface finish is examined as a solution for fine feature sizes in high frequency applications. The final paper studies lower cost finishes for IC substrates, covering processes and costs, as well as wire bonding and solderability.

Quality, Reliability and Metallurgy of ENEPIG Board Finish and Tin-Lead Solder Joints
Mike Wolverton, P.E., Raytheon Space & Airborne Systems

Electroless Pure Palladium Deposition on Copper as a Cu Wire Bondable Surface Finish
Mustafa Oezkoek, Gustavo Ramos, Arnd Kilian, Atotech Deutschland GmbH

A Study of Surface Finishes for IC Substrates and Wire Bond Applications
Ernest Long, Ph.D., Lenora Toscano, Speaker of Distinction

MacDermid, Inc.

WEDNESDAY, OCTOBER 19
2:00pm - 3:30pm

AAT7 Drop/Shock Reliability of BGAs/CSPs
Chair: Ahmer Syed, Amkor Technology
Co-Chair: Brian Toleno, Ph.D., Henkel Corporation
Wednesday, October 19 | 2:00pm - 3:30pm | 202B

Improving the drop/shock reliability of IC packages continues to remain a focus for the industry, especially for handheld and portable products. The papers in this session address this main objective by considering the material effect on improving the reliability. Specifically, these papers provide insight on how underfill materials, solder joint volume, and solder alloy compositions affect the performance of IC packages under drop/shock loading conditions.

Assembly and Reliability of Preform Underfilmed BGAs in Drop Test and Thermal Cycling
Andrew Mawer Speaker of Distinction

, Thomas Koschmieder, Ph.D. Speaker of Distinction

, Paul Galles, Freescale Semiconductor; Randy Anding, George Skevofilax, Tim Lippe, Flextronics International

Assembly Process Influence on Mechanical Test Performance of 0.4mm Pitch CSPs and LGA Components
Jeff Schake, DEK USA; Brian Roggeman, AREA Consortium, Universal Instruments Corporation

Drop Test Performance of BGA Assembly Using SAC105Ti Solder Sphere
Weiping Liu, Ning-Cheng Lee, Ph.D. Speaker of Distinction

, Indium Corporation; Simin Bagheri, Polina Snugovsky, Ph.D., Jason Bragg, Russell Brush, Blake Harper, Celestica International Inc.

SMT6 Critical Cleaning and the Environment
Chair: Linda Woody, Lockheed-Martin
Co-Chair: Jack Reinke, Kyzen Corporation
Wednesday, October 19 | 2:00pm - 3:30pm | 202C

Cleaning is making a comeback due to concerns over reliability and the increased densities of electronic assemblies. At the same time, environmental pressures are limiting cleaning options thus increasing the complexity of the processes. This session will describe the environmental considerations associated with cleaning along with criticality of cleaning new technologies such as Package on Package components.

Japanese Green Technologies for SMT
Daido Sawairi, Sawa Corporation; Michelle Ogihara, Seika Machinery, Inc.

Reducing Environmental Impact of Cleaning Electronic Assemblies: A Case Study
Steve Stach, Austin America Technology

Is Cleaning Critical to PoP Assemblies?
Harald Wack, Ph.D., Umut Tosun, ZESTRON America

MFX5 Developing a Robust Selective Soldering Process
Chair: Denis Barbini, Ph.D., Universal Instruments Corporation
Co-Chair: Peter Biocca, ITW Kester
Wednesday, October 19 | 2:00pm - 3:30pm | 202D

The development of a robust, stable selective soldering process requires one to characterize the impact of PCB design, material sets, and process parameters through experimental design. While selective soldering is a valuable, automated process, advancements in techniques and process knowledge are required for the optimum results. This session looks specifically at these challenges and provides the attendee with invaluable assets to improve their selective soldering manufacturing.

How Detailed Design Guidelines Can Improve Soldering Quality and Reduce Costs in Selective Through-hole Soldering Processes
Heike Schlessmann, Christian Ott Speaker of Distinction

, SEHO North America, Inc.

Are Selective Soldering Fluxes Reliable?
Gerjan Diepstraten, Cobar/Balver Zinn

Achieving Excellent Barrel Fill On Thermally Challenging Boards Using Selective Soldering
Thomas Shoaf, Joseph Clure, Plexus Manufacturing Solutions

SUB 4 PCB Creep Corrosion Mechanisms
Chair: Norm Armendariz, Texas Instruments
Co-Chair: Raiyo Aspandiar, Ph.D., Intel Corporation
Wednesday, October 19 | 2:00pm - 3:30pm | 204A

Creep corrosion is a mass transport process in which solid corrosion products (typically sulfide and chloride) migrate over a surface without the influence of an electric field. Creep corrosion is highly surface-specific and a given corrosion product can only migrate on a specific type surface. Recently, creep corrosion has been observed on printed circuit boards with lead-free surface finishes such as ImAg and OSP. This session will look at various ways to inhibit creep corrosion and an evaluation of various surface finishes under a harsh corrosive environment.

ENTEK OM: An OSP Alternative High Performance Final Finish
James Kenny, Karl Wengenroth, John Fudala, Melanie Rischka, Yung Herng Yau, Ph.D., Cookson Electronics Enthone

Comparison of Several PCB Final Finishes in a Mixed Flowing Gas Test Environment
Robert Veale, Rockwell Automation; James Trainor, OMG Electronic Chemicals, LLC

Inhibition of Creep Corrosion Using Plasma Deposited Fluoropolymer Coating
Andy Brooks, Siobhan Woollard, Gareth Hennighan, Timothy von Werne, Speaker of Distinction

Semblant Limited

PRC1 Non-destructive Inspection and Analysis Methods
Chair: Rob Rowland, RadiSys Corporation
Co-Chair: Ian Williams, Intel Corporation
Wednesday, October 19 | 2:00pm - 3:30pm | 104

The ability to inspect and analyze components, substrates, solder pastes and solder joints is an important capability for any assembly operation. On-going process monitoring helps prevent problems and failure analysis capability helps fix problems. Real time, non-destructive methods such as X-ray, acoustic micro-imaging and optical inspection are preferred for their ability to provide timely feedback without destroying the product. This session will cover advancements in these inspection and analysis methods from a user and supplier perspective.

The Implications of Recent Technology Advances for X-Ray Inspection in Electronics
David Bernard, Ph.D. Speaker of Distinction

, Keith Bryant, Nordson DAGE

Process Control Inspection of Surface Mounted Components Using Acoustic Micro Imaging
Janet E. Semmens, Sonoscan, Inc.

Methods of Determining Solder Paste Inspection Tolerance Settings
Johnny Chen,R. Sivam V. Rajoo, Marco Zhao, Wei Wen, Golden Xu, Ace Ning, Michael Xie, An Qi Zhao, Wei Bing Qian, Zhen (Jane) Feng, Ph.D., Murad Kurwa, Flextronics International, Inc.

WEDNESDAY, OCTOBER 19
4:00pm - 5:30pm

AAT8 Voids in Ball Grid Array Solder Joints: Aggravation and Policing
Chair: Thomas Koschmeider, Ph,D., Freescale Semiconductor
Co-Chair: Richard Coyle, Ph.D., Alcatel-Lucent
Wednesday, October 19 | 4:00pm - 5:30pm | 202B

Voids in final solder-joints from ball grid array packages are a common artifact in assembly. Analysis of growth and causes for occurrence allow for understanding how to minimize void aggravation. Finally, the percentage of voids present as individuals or sums can be used for policing assembly process robustness. Policing voids is an active topic in the industry with a wide range of opinions.

Characterization of Void Growth in BGA Solder Balls Through Two SMT Reflow Soldering Cycles
Alan Donaldson, Raiyo Aspandiar, Ph.D., Intel Corporation

Impact of SMT Process Parameters to Control BGA Process Voids During Board Assembly
Lei Nie, Ph.D., Alan Donaldson, Srinivasa Aravamudhan, Raiyo Aspandiar, Ph.D., Intel Corporation

The Last Will and Testament of the BGA Void
David Hillman Speaker of Distinction

, Dave Adams, Tim Pearson, Brittany Petrick, Rockwell Collins; John Travis, David Bernard, Ph.D. Speaker of Distinction

, Nordson DAGE

MFX6 Wave Soldering
Chair: Denis Jean, Plexus Corporation
Co-Chair: Chrys Shea, Shea Engineering Services
Wednesday, October 19 | 4:00pm - 5:30pm | 202D

Wave soldering has been the most prominent mass soldering process for through- hole components in high volume applications and often complements the SMT reflow process. The through-hole barrel fill for high complexity thick board assemblies continues to be a challenge in lead-free soldering process. The thermodynamics and fluid characteristic of the molten lead-free solder alloy requires wave soldering process and board design to be optimized to realize the most cost effective/high quality soldering process.

The Effect of Design Parameters on PTH Barrel Fill in High Complexity Assembly
Jinda Songninluck, P.E., Juthathip Fangkangwanwong, Teng Hoon Ng, John McMahon, Celestica Inc.

iNEMI Lead-Free Wave Soldering Project: An Investigation of Reliability of Through-Hole Electrical Interconnects
Denis Barbini, Ph.D. Speaker of Distinction

, Universal Instruments Corporation; Quyen Chu, Jabil Corporation; Denis Jean, Plexus Corporation; Stuart Longgood, Delphi Corporation; Keith Howell, Nihon Superior Co. Ltd.; Jian Miremadi, Hewlett-Packard Company

Design for Manufacturability of PTH Hole Fill in Thick Board with OSP Surface Finish
Shining Chang, Rocky Wang, Yu Xiang, IBM Corporation; Paul Wang, Ph.D., Speaker of Distinction

Mitac International Inc.

SUB5 Impact of PCB Surface Finishes on Reliability and Process Defects - Panel
FREE Beer and Pretzels! Chair: Srini Chada, Ph.D., Henkel Electronic Materials LLC
Co-Chair: Donald Banks, St. Jude Medical
Wednesday, October 19 | 4:00pm - 5:30pm | 204A

This elite panel brings together experts from OEM, EMS, PCB, and plating chemistry fields to discuss the very important role surface finishes play in PCBA manufacturing and reliability. We continue an on-going discussion on several old but puzzling topics (black pad, etc) that still persist, as well as a few newer enigmas like tin whiskers. Panelists not only throw light on the aforementioned topics, but encourage open discussion with audience participation.

Panelists:

Rob Rowland, RadiSys

David Hillman, Rockwell Collins

Mustafa Oezkoek, Atotech GmbH

Lenora Toscano, MacDermid

Polina Snugovsky, Ph.D., Celestica Inc.

Lenora Toscano, MacDermid Mustafa Oezkoek, Atotech GmbH

THURSDAY, OCTOBER 20
8:00am - 10:00am

LF1 NASA-DoD Lead-Free Electronics Project: Project Overview and Update
Chair: Paul Vianco, Ph.D., Sandia National Laboratories
Co-Chair: Matt Kelly, P. Eng., MBA, IBM Corporation
Thursday, October 20 | 8:00am - 10:00am | 204A/B

The NASA-DoD Lead-Free Electronics Project brings together experts from electronics communities in an intensive test program that is examining the reliability of Pb-free solder interconnections. The study incorporates many of the current technical drivers in a Pb-free conversion, including the solder alloy selection, surface finish, and the impact or repair and rework on the integrity of electronic packaging and interconnections. A brief overview will be presented, which describes the tasks and deliverable of the NASA-DoD project for the attendee. Also, the technical results will be presented from two important assessments: (a) effect of rework on vibration reliability and (b) -20°C/80°C thermal cycling tests. These individual test programs are critical to the implementation of Pb-free technology in high-reliability commercial and military electronics

NASA-DoD Lead-Free Electronics Rework Project: Effect of 1X and 2X Eutectic Solder Rework on Vibration Reliability
J. P. Tucker, C. A. Handwerker, Ph.D., Purdue University; W. Russell, Raytheon; D. D. Fritz, SAIC; A. Ganster, Crane Division-NSWC; P. Snugovsky, Ph.D., J. Bragg, Z. Bagheri, M. Romansky, Celestica Inc.

NASA/DoD Lead-Free Electronics Project: -20°C to +80°C Thermal Cycle Test
Thomas Woodrow, Ph.D. Speaker of Distinction

, Boeing

NASA-DoD Lead-Free Electronics Project - Joint Test Report
Kurt Kessel, NASA TEERM (ITB, Inc.); David Hillman Speaker of Distinction

, Rockwell Collins

NASA-DoD Lead-Free Electronics Project - Joint Test Report - continued

THURSDAY, OCTOBER 20
10:30am - 12:00pm

LF2 Investigating the Edges of Lead-Free Assembly Processes
Chair: David Hillman, Rockwell Collins
Co-Chair: Keith Sweatman, Nihon Superior Co., Ltd.
Thursday, October 20 | 10:30am - 12:00pm | 204A/B

The electronics industry has been successfully characterizing and qualifying the various aspects of lead-free solder processes for several years. Baseline material sets and process parameters have been established for a number industry product segments. However, there are numerous portions of the lead-free soldering processes that are now just getting industry attention. This session will provide an attendee insight into lead-free plated thru hole rework, lead-free vapor phase assembly and lead-free product qualification.

Lead-Free Solder Assembly Implementation for a Mid-Range Power Systems Server
P. K. Pu, IBM China Procurement Limited; Theron Lewis, Marie Cole Speaker of Distinction

, Mark Hoffmeyer, John Shaughnessey, Tom Finck, Mark Stevens, Kari Fischer, Joe Doman, IBM Corporation

Lead-Free Vapor Phase Assembly Compatible Materials for a High Performance SMT Backplane Connector
Matthew Kelly, P.Eng., MBA Speaker of Distinction

, Ying Yu, John Healey, Emanuele Lopergolo, Jing Zhang, Jay Diepenbrock, Theron Lewis, Vijay Khanna, Ruediger Kellmann, Jim Bielick, IBM Corporation

Challenges and Developments for Lead-Free Wave Rework Soldering
Sunil Gopakumar, Ph.D., Francois Billaut, Eric Fremd, Brocade Communications; K. Y. Tsai, Chu Lin, Foxconn; Jasbir Bath Speaker of Distinction

, Brocade, FoxConn, and Bath Technical Consultancy

THURSDAY, OCTOBER 20
12:00pm - 1:30pm

Lead-Free Keynote Lunch
Chair: Matt Kelly, P. Eng., MBA, IBM Corporation

Thursday, October 20 | 12:00pm - 1:30pm | 204A/B

Programmatic Challenges of Pb-Free Technology for the High-Reliability Electronics Industry
Paul Vianco, Ph.D. Speaker of Distinction

, Sandia National Laboratories

THURSDAY, OCTOBER 20
1:30pm - 3:00pm

LF3 Mechanical Reliability Performance of Lead-Free Solder Alloys
Chair: Matt Kelly, P. Eng., MBA, IBM Corporation
Co-Chair: Richard Coyle, Ph.D., Alcatel-Lucent
Thursday, October 20 | 1:30pm - 3:00pm | 204A/B

Although much of the industry continues to focus on thermal fatigue wear-out performance of new lead-free solder joints, for many applications it is equally important to understand resultant mechanical reliability performance of interconnect structures. This session focuses on mechanical reliability issues and performance comparisons during PCB pad cratering assessment and high strain rate mechanical shock test protocols.

Material Testing and Mitigation Techniques for Pad Crater Defects
Brian Gray, P.E., John McMahon, Celestica Inc.

Reliability Impact of Partial Pad Craters
Brian Roggeman, David Rae, AREA Consortium, Universal Instruments Corporation

Stress-Strain Behavior of SnAgCu Lead-Free Alloys at High Strain Rates Typical of Mechanical Shock
Pradeep Lall, Ph.D., MBA Speaker of Distinction

, Sandeep Shantaram, Mandar Kulkarni, Geeta Limaye, Jeff Suhling, Auburn University

THURSDAY, OCTOBER 20
3:30pm - 5:00pm

LF4 Lead-Free Solder Joint Reliability: Impact of Alloy Composition, Design and Load Parameters
Chair: Jean-Paul Clech, Ph.D., EPSI, Inc.
Co-Chair: Kola Akinade, Ph.D., Cisco Systems
Thursday, October 20 | 3:30pm - 5:00pm | 204A/B

This session highlights recent progress in the understanding of lead-free solder joint reliability under thermal cycling conditions. A wide range of accelerated test data is presented that is of use to assess the effect of both pre-conditioning (aging) and thermal cycling profiles on SnAgCu (SAC) assembly reliability. Pros and cons of various lead-free acceleration factors - which are badly needed to extrapolate test failure data to field conditions - are discussed, including recent improvements developing more reliable acceleration factor models.

Assessment of Sn-3.0Ag-0.5Cu Solder Joints Submitted to Different Thermal Cycling
Olivier Maire, Ph.D., EADS Innovation Works: S. Bousquet, Airbus; M. Tran, Airbus EDYY; C. Gil, MBDA; N. Wazad, Eurocoptor; M. Jeremias, Astrium Satellites; T. Backes, Cassidian; M. Jeremias, Sodeern

Variations in Thermal Cycling Response of Pb-free Solder Due to Isothermal Preconditioning
Joseph Smetana, Richard Coyle, Ph.D. Speaker of Distinction

, Peter Read, Richard Popowich, Alcatel-Lucent; Thilo Sack, Celestica Inc.

Damage Mechanism Based Acceleration Factor Model for Pb-Free Solder
Ahmer Syed, Amkor Technology

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